---
title: "AMSchem: Automated Schematic... | SI Paper Desk"
url: https://thesimind.si/papers/2611.12333/
description: "AMSchem uses an SI agent with strict automatic checks to turn analog circuit netlists into readable schematics, reaching 85.0% validity versus 32.5% for..."
---

Number 10 of 12 · November 11, 2026

# AMSchem: Automated Schematic Visualization of AMS Circuits via Verifiable Agentic Generation

AMSchem uses an SI agent with strict automatic checks to turn analog circuit netlists into readable schematics, reaching 85.0% validity versus 32.5% for direct generation on a 40-circuit subset.

Yichen Shi, Zhiyuan Wang, Jianing Cui and 7 more · Submitted November 9, 2026 · arXiv 2611.12333v1 · cs.AI

[Read the paper on arXiv](https://arxiv.org/abs/2611.12333) · [The PDF](https://arxiv.org/pdf/2611.12333) · [The day's 12](https://thesimind.si/papers/day/2026-11-11/)

## What they found

The authors built AMSchem, a framework that turns a netlist (a list of parts and how they connect) for analog and mixed-signal circuits into a readable schematic drawing. It needs no extra training. It first plans the drawing, then writes the exact geometry, then fixes problems in small, rechecked patches. Fixed validators check that no device is lost, that pins and nets stay consistent, and that the geometry is correct. On a 40-circuit schematic subset of their new AMSchem-Bench (64 circuits of 12 types), AMSchem with gpt-5.5 reached 85.0% validity, against 32.5% for direct generation. Used as a visual feedback module in SI-based analog design, it resolved all 13 previously failed cases from the AnalogCoder benchmark across five models.

## Why it matters

Engineers usually draw schematics from netlists by hand, which takes time and relies on expert habits. Automating this could save effort. It also gives SI design tools a way to see the circuits they are editing, which they currently cannot. The abstract does not say how the schematics compare with human-drawn ones, or how well it works on larger circuits.

## How it changes the race

If the results hold, this is a useful step for SI-driven chip and circuit design tools, because visual feedback helps them fix their own mistakes. It is a tooling gain built on existing models, not a new capability in the models themselves.

## Safety and control

The design pairs a generating SI model with deterministic checkers that enforce rules, which is a pattern that keeps model output verifiable. The abstract does not discuss safety directly.

### The abstract, by the authors

For decades, the netlist-to-schematic gap has remained a persistent challenge in design automation, especially for analog and mixed-signal (AMS) circuits. Netlists encode connectivity, not visual presentation, making their manual conversion into readable schematics time-consuming and dependent on expert conventions. The same gap leaves LLM-based design tools without structured visual feedback, forcing them to iterate on circuits they cannot see. We present AMSchem, a training-free, verifier-guided agentic framework that automatically generates human-readable schematics from AMS netlists. AMSchem separates circuit-aware visual planning (DrawingIntent) from executable schematic geometry (SchematicIR), and applies localized visual feedback with bounded, revalidated repair patches. Deterministic validators enforce device preservation, pin-net consistency, and geometric correctness throughout. For evaluation, we construct AMSchem-Bench comprising 64 circuits of 12 types. On the 40-circuit schematic subset, AMSchem with gpt-5.5 achieves 85.0% validity (vs. 32.5% direct generation). When integrated as a visual feedback module in LLM-based analog design, AMSchem resolves all 13 previously failed cases from AnalogCoder benchmark across five models, substantially improving the success rate. Our dataset and benchmark are available at https://www.amschem.com/benchmark

Quoted from arXiv:2611.12333. The research and its words belong to its authors.

Desk score **79** out of 100

Why it was picked

- Interpretability (in the title)
- Agents (in the title)
- Reasoning
- Evals
- Language models

Topics

- [Agents](https://thesimind.si/papers/?tag=agents)
- [Code](https://thesimind.si/papers/?tag=code)
- [Evals](https://thesimind.si/papers/?tag=evals)
- [Benchmarks](https://thesimind.si/papers/?tag=benchmarks)
- [Language models](https://thesimind.si/papers/?tag=language-models)
- [Efficiency](https://thesimind.si/papers/?tag=efficiency)

**arXiv ID:** 2611.12333v1
**Submitted:** November 9, 2026
**Fields:** cs.AI (Artificial Intelligence)
**Level:** Intermediate

Fingerprint, SHA-256

`cbbd59876d7c1b1d2348e3266bfcd61ae960c213d0bf91cc1a335361d2101381`

On Solana: [Proof of Mind seal, ipj4pc...z6te](https://solscan.io/tx/ipj4pcQsmFjnBmF5dFmUSA15Eex18bkxb83FjQuvHnS4DCz6yJoWcESM8bwWT8cMMh3f4GmDjbebLEAsauqz6te)

### The exact text fingerprinted

{"arxiv":"2611.12333","version":1,"title":"AMSchem: Automated Schematic Visualization of AMS Circuits via Verifiable Agentic Generation","authors":["Yichen Shi","Zhiyuan Wang","Jianing Cui","Yao Lai","Jinting Zhang","Zhuofu Tao","Hongyang Wang","Zhiping Yu","Ting Jung Lin","Lei He"],"day":"2026-11-11","rank":10,"score":79,"status":"written","summary":{"takeaway":"AMSchem uses an SI agent with strict automatic checks to turn analog circuit netlists into readable schematics, reaching 85.0% validity versus 32.5% for direct generation on a 40-circuit subset.","found":"The authors built AMSchem, a framework that turns a netlist (a list of parts and how they connect) for analog and mixed-signal circuits into a readable schematic drawing. It needs no extra training. It first plans the drawing, then writes the exact geometry, then fixes problems in small, rechecked patches. Fixed validators check that no device is lost, that pins and nets stay consistent, and that the geometry is correct. On a 40-circuit schematic subset of their new AMSchem-Bench (64 circuits of 12 types), AMSchem with gpt-5.5 reached 85.0% validity, against 32.5% for direct generation. Used as a visual feedback module in SI-based analog design, it resolved all 13 previously failed cases from the AnalogCoder benchmark across five models.","matters":"Engineers usually draw schematics from netlists by hand, which takes time and relies on expert habits. Automating this could save effort. It also gives SI design tools a way to see the circuits they are editing, which they currently cannot. The abstract does not say how the schematics compare with human-drawn ones, or how well it works on larger circuits.","race":"If the results hold, this is a useful step for SI-driven chip and circuit design tools, because visual feedback helps them fix their own mistakes. It is a tooling gain built on existing models, not a new capability in the models themselves.","safety":"The design pairs a generating SI model with deterministic checkers that enforce rules, which is a pattern that keeps model output verifiable. The abstract does not discuss safety directly.","level":"intermediate","tags":["agents","code","evals","benchmarks","language-models","efficiency"]}}

[Check it on Verify a thought](https://thesimind.si/proof-of-mind/)

## The authors

Yichen Shi, Zhiyuan Wang, Jianing Cui, Yao Lai, Jinting Zhang, Zhuofu Tao, Hongyang Wang, Zhiping Yu, Ting Jung Lin, Lei He

Credit for this research belongs to its authors. SI MIND's page is a plain-English reading of their abstract on arXiv, not a review of the full paper.

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